Poseidon emulates an 82C54 counter/timer chip, providing 3 16-bit counter/timers.
Counters 1 and 2 are cascaded together to form a 32-bit counter/timer for use as a programmable A/D sampling clock. The output of counter 1 provides the input for counter 2, and the output of counter 2 is fed to the A/D triggering circuit as well as the I/O header CN12. If not being used for A/D sampling, these counter/timers may be used for other functions. Counter/timer 0 is always available for user applications.
The inputs of the counter/timers are programmable, and the outputs may be routed to the I/O header under software control. The table, below, lists the key features of each counter/timer.
| Counter | Input | Gate | Output |
| 0 |
|
DIN1/GATE0 (CN12, pin 26) | DOUT0/CTROUT0 (CN12, pin 27) |
| 1 |
|
DIN2/EXTGATE (CN12, pin 32) | Not available |
| 2 | DIN2/EXTGATE (CN12, pin 32) |
|
The counter/timer configuration is determined by the control register at Base+10. Note that the outputs of counters 0 and 2 are routed to pins on I/O header CN12 under software control rather than being hardwired.
Configuring the A/D sampling clock is done with the control register at Base+9. Bit CLKEN selects whether or not the A/D hardware clocking is enabled. If clocking is enabled, bit CLKSEL selects whether or not it is the output of counter/timer 2 or the external clock input at DIN3/EXTCLK, on CN12.
Before performing any access to the chip, you must set the current page to page 0 with the miscellaneous control register at Base+8 to ensure that the proper page is enabled. Note that writing page bits to the miscellaneous control register does not cause a board reset or interrupt reset operation as long as the two reset bits are left at 0. Also, writing a 1 to either reset bit in this register does not change the contents of the page bits.
The current page may be determined by reading the page bits at Base+7.
Once you write the proper page value, you can read and write to the 82C54 registers.