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Products   >   I/O Expansion Modules   >   Digital I/O Modules   >   GPIO-MM-21 PC/104 Digital I/O Module
FEATURES
96 programmable digital I/O lines based on 8255 cores
3 pin headers for a total of 100 I/O pins
Based on a Xilinx Spartan II RAM-based FPGA for field reconfigurability FPGA personality display for easy identification
-40°C to +85°C operation
PC/104 form factor
FREE Universal Driver software included
ONLINE SUPPORT
Product Documentation
Software Downloads
Discussion Topics
Frequently Asked Questions
Request Product information
Request Technical Support
DOWNLOADS
GPIO-MM Datasheet
(.pdf, 277.6 kb)
GPIO-MM FPGA Pinout Guide
(.pdf, 331.4 kb)
GPIO-MM Personality Guide v1.01
(.pdf, 239.5 kb)
GPIO-MM-21 User Manual
(.pdf, 363.8 kb)
Universal Driver Reference Manual
(.html, 0.6 kb)
Universal Driver 6.02 Release Notes
(.pdf, 141.3 kb)
Universal Driver 6.02 for DOS
(.zip, 176.5 kb)
Universal Driver 6.02 for Linux
(.bz2, 148.3 kb)
Universal Driver 6.02 for QNX
(.bz2, 121.8 kb)
Universal Driver 6.02 for Windows CE
(.zip, 106.7 kb)
Universal Driver 6.02 for Windows XP
(.zip, 331.8 kb)

GPIO-MM-21 PC/104 Digital I/O Module

Reconfigurable 96-line Digital I/O PC/104 Module

GPIO-MM-21 PC/104 Digital I/O Module
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Description
Block Diagram
I/O headers
Specifications
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Description

GPIO-MM-21 is part of a family of reconfigurable digital I/O and counter / timer modules with various port and pin configurations. Each board uses identical hardware with a 200K gate Xilinx Spartan II RAM-based FPGA. The varying configurations are based on different FPGA code. The FPGA code is stored in a flash memory on the board, enabling GPIO-MM-21 to be reprogrammed in the field with different designs, including custom designs.

The GPIO-MM-21 configuration provides 96 digital I/O lines. 48 lines are buffered. The 96 digital I/O lines are compatible with our legacy Garnet-MM and Onyx-MM boards. This configuration combines the features of two 48-line digital I/O boards into one board to reduce your PC/104 stack size and cost.

Other GPIO-MM configurations provide 48 digital I/O lines with 10 16-bit counter/timers.

Digital I/O Features

The digital I/O includes 96 programmable-direction lines using four 8255 cores. 48 of the I/O lines are buffered for enhanced output current. All I/O lines contain jumper-selectable 10Kohm pull-up/pull-down resistors. 48 I/O lines are contained on each of two 50-pin connectors, along with system ground and a convenient +5V power pin. Both I/O connectors provide the digital I/O lines in ABC port order.

Miscellaneous Features

The board requires only a +5V input and operates from -40°C to +85°C. All board functions are supported by our Universal Driver software for Linux, Windows 2000/XP/CE, DOS, and QNX.

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I/O Headers

GPIO-MM-21 Pin Definition

J3 Unbuffered Digital I/O

Port7 7 1 2 Port10 7
Port7 6 3 4 Port10 6
Port7 5 5 6 Port10 5
Port7 4 7 8 Port10 4
Port7 3 9 10 Port10 3
Port7 2 11 12 Port10 2
Port7 1 13 14 Port10 1
Port8 0 15 16 Port10 0
Port8 7 17 18 Port11 7
Port8 6 19 20 Port11 6
Port8 5 21 22 Port11 5
Port8 4 23 24 Port11 4
Port8 3 25 26 Port11 3
Port8 2 27 28 Port11 2
Port8 1 29 30 Port11 1
Port8 0 31 32 Port11 0
Port9 7 33 34 Port12 7
Port9 6 35 36 Port12 6
Port9 5 37 38 Port12 5
Port9 4 39 40 Port12 4
Port9 3 41 42 Port12 3
Port9 2 43 44 Port12 2
Port9 1 45 46 Port12 1
Port9 0 47 48 Port12 0
+5V 49 50 Ground

J4 Buffered Digital I/O

Port1 7 1 2 Port4 7
Port1 6 3 4 Port4 6
Port1 5 5 6 Port4 5
Port1 4 7 8 Port4 4
Port1 3 9 10 Port4 3
Port1 2 11 12 Port4 2
Port1 1 13 14 Port4 1
Port1 0 15 16 Port4 0
Port2 7 17 18 Port5 7
Port2 6 19 20 Port5 6
Port2 5 21 22 Port5 5
Port2 4 23 24 Port5 4
Port2 3 25 26 Port5 3
Port2 2 27 28 Port5 2
Port2 1 29 30 Port5 1
Port2 0 31 32 Port5 0
Port3 7 33 34 Port6 7
Port3 6 35 36 Port6 6
Port3 5 37 38 Port6 5
Port3 4 39 40 Port6 4
Port3 3 41 42 Port6 3
Port3 2 43 44 Port6 2
Port3 1 45 46 Port6 1
Port3 0 47 48 Port6 0
+5V 49 50 Ground

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Specifications

Base FPGA Xilinx Spartan II, 200,000 gates, 40K RAM bits
Input clock 40MHz
FPGA code storage Flash memory, field upgradeable via JTAG
ID indicator 8-bit LED display indicates FPGA code personality
No. of I/O pins 100 pins (48 buffered)
Programmable Digital I/O 96 using 8255 cores
Output current, buffered I/O Logic 0: 64mA max per line
Dimensions 3.55" x 3.775", PC/104 form factor
PC/104 bus 16-bit stackthrough ISA bus
Power supply +5VDC ±5%
Operating temperature -40°C to +85°C standard, all versions
RoHS Compliant

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GPIO-MM-21 PC/104 Digital I/O Module
available models:
GPIO-MM-21-XT
96 Digital I/O PC/104 Module
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Cables and accessories
available models:
C-50-18
50-conductor .1" pitch 18" ribbon cable Data Acquisition
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