GPIO-MM-21
Reconfigurable 96-line Digital I/O PC/104 Module
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Description |
GPIO-MM-21 is part of a family of reconfigurable digital I/O and counter / timer modules with various port and pin configurations. Each board uses identical hardware with a 200K gate Xilinx Spartan II RAM-based FPGA. The varying configurations are based on different FPGA code. The FPGA code is stored in a flash memory on the board, enabling GPIO-MM-21 to be reprogrammed in the field with different designs, including custom designs.
The GPIO-MM-21 configuration provides 96 digital I/O lines. 48 lines are buffered.
The 96 digital I/O lines are compatible with our legacy Garnet-MM and Onyx-MM
boards. This configuration combines the features of two 48-line digital I/O
boards into one board to reduce your PC/104 stack size and cost.
Other GPIO-MM configurations provide 48 digital I/O lines with 10 16-bit counter/timers.
Digital I/O Features
The digital I/O includes 96 programmable-direction lines using four 8255 cores. 48 of the I/O lines are buffered for enhanced output current. All I/O lines contain jumper-selectable 10Kohm pull-up/pull-down resistors. 48 I/O lines are contained on each of two 50-pin connectors, along with system ground and a convenient +5V power pin. Both I/O connectors provide the digital I/O lines in ABC port order.
Miscellaneous Features
The board requires only a +5V input and operates from -40°C to +85°C.
All board functions are supported by our Universal Driver software for Linux,
Windows 98/2000/XP/CE.NET, DOS, QNX, and VxWorks.
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I/O Headers |
GPIO-MM-21 Pin Definition
J3 Digital I/O
| Port 3A7 |
1 |
2 |
Port 4A7 |
| Port 3A6 |
3 |
4 |
Port 4A6 |
| Port 3A5 |
5 |
6 |
Port 4A5 |
| Port 3A4 |
7 |
8 |
Port 4A4 |
| Port 3A3 |
9 |
10 |
Port 4A3 |
| Port 3A2 |
11 |
12 |
Port 4A2 |
| Port 3A1 |
13 |
14 |
Port 4A1 |
| Port 3A0 |
15 |
16 |
Port 4A0 |
| Port 3B7 |
17 |
18 |
Port 4B7 |
| Port 3B6 |
19 |
20 |
Port 4B6 |
| Port 3B5 |
21 |
22 |
Port 4B5 |
| Port 3B4 |
23 |
24 |
Port 4B4 |
| Port 3B3 |
25 |
26 |
Port 4B3 |
| Port 3B2 |
27 |
28 |
Port 4B2 |
| Port 3B1 |
29 |
30 |
Port 4B1 |
| Port 3B0 |
31 |
32 |
Port 4B0 |
| Port 3C7 |
33 |
34 |
Port 4C7 |
| Port 3C6 |
35 |
36 |
Port 4C6 |
| Port 3C5 |
37 |
38 |
Port 4C5 |
| Port 3C4 |
39 |
40 |
Port 4C4 |
| Port 3C3 |
41 |
42 |
Port 4C3 |
| Port 3C2 |
43 |
44 |
Port 4C2 |
| Port 3C1 |
45 |
46 |
Port 4C1 |
| Port 3C0 |
47 |
48 |
Port 4C0 |
| +5V |
49 |
50 |
Ground |
J4 Digital I/O
| Port 1A7 |
1 |
2 |
Port 2A7 |
| Port 1A6 |
3 |
4 |
Port 2A6 |
| Port 1A5 |
5 |
6 |
Port 2A5 |
| Port 1A4 |
7 |
8 |
Port 2A4 |
| Port 1A3 |
9 |
10 |
Port 2A3 |
| Port 1A2 |
11 |
12 |
Port 2A2 |
| Port 1A1 |
13 |
14 |
Port 2A1 |
| Port 1A0 |
15 |
16 |
Port 2A0 |
| Port 1B7 |
17 |
18 |
Port 2B7 |
| Port 1B6 |
19 |
20 |
Port 2B6 |
| Port 1B5 |
21 |
22 |
Port 2B5 |
| Port 1B4 |
23 |
24 |
Port 2B4 |
| Port 1B3 |
25 |
26 |
Port 2B3 |
| Port 1B2 |
27 |
28 |
Port 2B2 |
| Port 1B1 |
29 |
30 |
Port 2B1 |
| Port 1B0 |
31 |
32 |
Port 2B0 |
| Port 1C7 |
33 |
34 |
Port 2C7 |
| Port 1C6 |
35 |
36 |
Port 2C6 |
| Port 1C5 |
37 |
38 |
Port 2C5 |
| Port 1C4 |
39 |
40 |
Port 2C4 |
| Port 1C3 |
41 |
42 |
Port 2C3 |
| Port 1C2 |
43 |
44 |
Port 2C2 |
| Port 1C1 |
45 |
46 |
Port 2C1 |
| Port 1C0 |
47 |
48 |
Port 2C0 |
| +5V |
49 |
50 |
Ground |
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Specifications |
| Base FPGA |
Xilinx Spartan II, 200,000 gates, 40K RAM bits |
| Input clock |
40MHz |
| FPGA code storage |
Flash memory, field upgradeable via JTAG |
| ID indicator |
8-bit LED display indicates FPGA code personality |
| No. of I/O pins |
100 pins (48 buffered) |
| Programmable Digital I/O |
96 using 8255 cores |
| Output current, buffered I/O |
Logic 0: 64mA max per line |
| Dimensions |
3.55" x 3.775", PC/104 form factor |
| PC/104 bus |
16-bit stackthrough ISA bus |
| Power supply |
+5VDC ±5% |
| Operating temperature |
-40°C to +85°C standard, all versions |
| RoHS |
Compliant |
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GPIO-MM-21 |
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| 96 Digital I/O PC/104 Module |
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Cables and accessories |
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| 50-conductor .1" pitch 18" ribbon cable Data Acquisition |
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Copyright© Diamond Systems Corporation 2001-2009. All rights reserved.
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