Data Acquisition Circuit

Poseidon integrated data acquisition functions incorporate the same circuitry as the DMM-32X-AT PC/104 module. Poseidon utilizes Diamond Systems’ patented Automatic Auto-calibration technology to calibrate the A/D and D/A circuits automatically when required, without user intervention. Auto-calibration provides analog I/O performance with the maximum possible accuracy over the life of the product.

If using Diamond Systems Universal Driver (DSCUD), develop code in the same way as for the DMM-32X-AT. The code developed for the DMM-32X-AT runs with no change on Poseidon, with the exception that the Poseidon DAQ does not have an equivalent to the DMM-32X-AT serial port.

Poseidon has the following Data Acquisition Circuit features.

32 analog inputs with 16-bit A/D and 250KHz sample rate

4 analog outputs with 12-bit D/A and 100KHz waveform output capability

24 digital I/O lines

2 counter/timers

interrupt and DMA A/D transfers, using an enhanced 1,024-sample FIFO with programmable threshold

Note: Diamond Systems free Universal Driver software for Linux, Windows 98/2000/XP/CE.NET, DOS, QNX, and VxWorks is available for programming the board.

Figure 1 shows a block diagram of the data acquisition circuit.

Figure 1: Data Acquisition Block Diagram

Data Acquisition Circuitry I/O Map

I/O Memory Space

Poseidon occupies 16 bytes in the system I/O address space. Registers 12 through 15 provide paged windows for access to additional registers without requiring additional I/O address space.

The following tables list the register functions and base address offset, for each page.

Note: Control bits in register 8 are used for page selection.

Main Register Set
Base +	Write Function	Read Function
0	Start A/D Conversion	A/D LSB (bits 7-0)
1	Auxiliary Digital Output	A/D MSB (bits 15-8)
2	A/D Low Channel	A/D low Channel Read-back
3	A/D high Channel	A/D high Channel Read-back
4	DAC LSB	Status/Auxiliary Digital Input
5	DAC MSB + Channel	FIFO Threshold Read-back (bit 8)
6	FIFO Threshold	FIFO Threshold Read-back (bits 7-0)
7	FIFO Control	FIFO Status
8	Miscellaneous and Page Control	A/D Status
9	Interrupt and A/D Clock Control	Interrupt and A/D Clock Status
10	Counter/Timer and DIO Control	C/T and DIO Control Read-back
11	Analog Configuration	Analog I/O Read-back

Page 0 - 82C54 Counter/Timer Access
Base +	Write Function	Read Function
12	Counter 0 Data	Counter 0 Data Read-back
13	Counter 1 Data	Counter 1 Data Read-back
14	Counter 2 Data	Counter 2 Data Read-back
15	82C54 Control	82C54 Control Read-back

Page 1 - 82C55-Type Digital I/O
Base +	Write Function	Read Function
12	DIO Port A Output	DIO Port A Input
13	DIO Port B Output	DIO Port B Input
14	DIO Port C Output	DIO Port C Input
15	DIO Control	DIO Control Read-back

Page 2 - FIFO Control (Enhanced Feature Page)
Base +	Write Function	Read Function
12	Expanded FIFO Depth	Expanded FIFO Depth Read-back
13	-	-
14	-	-
15	-	-

Page 3 - Autocalibration Registers
Base +	Write Function	Read Function
12	EEPROM/TrimDAC Data	EEPROM/TrimDAC Data Read-back
13	EEPROM/TrimDAC Address	EEPROM/TrimDAC Address Read-back
14	Calibration Control	Calibration Status
15	Advanced Feature Access	FPGA Revision Code

Page 4 - dsPIC Interface (Enhanced Feature Page)
Base +	Write Function	Read Function
12	dsPIC Data	dsPIC Data
13	dsPIC Address	dsPIC Address Read-back
14	Auto-calibration Command	Auto-calibration Status
15	dsPIC Programming Control	dsPIC Programming Status

Page 5 - D/A Waveform Generator (Enhanced Feature Page)
Base +	Write Function	Read Function
12	Waveform Buffer Address (LSB)	-
13	Waveform Buffer Address (MSB)	-
14	Waveform Generator Control	Waveform Generator Control Read-back
15	Waveform Generator Command	-

Note: Page 6, CPLD I/O Window (Enhanced Feature Page), is a window to the CPLD I/O. This page should not be accessed in normal operation.

I/O Register Summary

Write Register Definitions

Base +	7	6	5	4	3	2	1	0
Main Register Set
0	ADSTART
1	-	-	-	-	LED	DOUT2	DOUT1	DOUT0
2	-	-	-	L4	L3	L2	L1	L0
3	-	-	-	H4	H3	H2	H1	H0
4	DA7	DA6	DA5	DA4	DA3	DA2	DA1	DA0
5	DACH1	DACH0	DASIM	DAGEN	DA11	DA10	DA9	DA8
6	FD8	FD7	FD6	FD5	FD4	FD3	FD2	FD1
7	-	-	-	-	FIFOEN	SCANEN	FIFORST	-
8	-	-	RESETA	RESETD	INTRST	P2	P1	P0
9	ADINTE	DINTE	TINTE	RSVD1	DMAEN	-	CLKEN	CLKSEL
10	FREQ12	FREQ0	OUT2EN	OUT0EN	RSVD	GT0EN	SRC0	GT12EN
11	-	-	SCINT1	SCINT0	RANGE	ADBU	G1	G0
Page 0 - 82C54 Counter/Timer Access
12	CTR0D7	CTR0D6	CTR0D5	CTR0D4	CTR0D3	CTR0D2	CTR0D1	CTR0D0
13	CTR1D7	CTR1D6	CTR1D5	CTR1D4	CTR1D3	CTR1D2	CTR1D1	CTR1D0
14	CTR2D7	CTR2D6	CTR2D5	CTR2D4	CTR2D3	CTR2D2	CTR2D1	CTR2D0
15	SC1	SC0	RW1	RW0	M2	M1	M0	BCD
Page 1 - 82C55-Type Digital I/O
12	A7	A6	A5	A4	A3	A2	A1	A0
13	B7	B6	B5	B4	B3	B2	B1	B0
14	C7	C6	C5	C4	C3	C2	C1	C0
15	1	MODEC	MODEA	DIRA	DIRCH	MODEB	DIRB	DIRCL
Page 2 - FIFO Control (Enhanced Feature Page)
12	-	-	-	-	-	-	-	FD9
Page 3 - Autocalibration Registers
12	D7	D6	D5	D4	D3	D2	D1	D0
13	-	A6	A5	A4	A3	A2	A1	A0
14	EE_EN	EE_RW	RUNCAL	MUXEN	TDACEN	-	-	-
15	EE_ACC
Page 4 - dsPIC Interface (Enhanced Feature Page)
12	PICD7	PICD6	PICD5	PICD4	PICD3	PICD2	PICD1	PICD0
13	PICR/W	-	-	PICA4	PICA3	PICA2	PICA1	PICA0
14	-	-	-	ACHOLD	ACREL	PICRST	ACABT	ACTRIB
15	PSTART	PSTOP	PGDOUT	PGDIN	PGDW1	PGDW0	PGCW1	PGCW0
Page 5 - D/A Waveform Generator (Enhanced Feature Page)
12	DACA7	DACA6	DACA5	DACA4	DACA3	DACA2	DACA1	DACA0
13	-	-	-	-	-	-	DACA9	DACA8
14	DEPTH3	DEPTH2	DEPTH1	DEPTH0	WGCH1	WGCH0	WGSRC1	WGSRC0
15	-	-	-	-	WGINC	WGRST	WGPS	WGSTRT

Read Register Definitions

Base +	7	6	5	4	3	2	1	0
Main Register Set
0	AD7	AD6	AD5	AD4	AD3	AD2	AD1	AD0
1	AD15	AD14	AD13	AD12	AD11	AD10	AD9	AD8
2	-	-	-	L4	L3	L2	L1	L0
3	-	-	-	H4	H3	H2	H1	H0
4	DACBUSY	CALBUSY	ACACT	-	DIN3	DIN2	DIN1	DIN0
5	-	-	-	-	-	-	-	FD9
6	FD8	FD7	FD6	FD5	FD4	FD3	FD2	FD1
7	EF	TF	FF	OVF	FIFOEN	SCANEN	PAGE1	PAGE0
8	STS	S/D1	S/D0	ADCH4	ADCH3	ADCH2	ADCH1	ADCH0
9	ADINT	DINT	TINT	-	DMAEN	P2	CLKEN	CLKSEL
10	FREQ12	FREQ0	OUT2EN	OUT0EN	RSVD	GT0EN	SRC0	GT12EN
11	WAIT	RSVD	SCINT1	SCINT0	RANGE	ADBU	G1	G0
Page 0 - 82C54 Counter/Timer Access
12	CTR0D7	CTR0D6	CTR0D5	CTR0D4	CTR0D3	CTR0D2	CTR0D1	CTR0D0
13	CTR1D7	CTR1D6	CTR1D5	CTR1D4	CTR1D3	CTR1D2	CTR1D1	CTR1D0
14	CTR2D7	CTR2D6	CTR2D5	CTR2D4	CTR2D3	CTR2D2	CTR2D1	CTR2D0
15	SC1	SC0	RW1	RW0	M2	M1	M0	BCD
Page 1 - 82C55-Type Digital I/O
12	A7	A6	A5	A4	A3	A2	A1	A0
13	B7	B6	B5	B4	B3	B2	B1	B0
14	C7	C6	C5	C4	C3	C2	C1	C0
15	1	MODEC	MODEA	DIRA	DIRCH	MODEB	DIRB	DIRCL
Page 2 - FIFO Control (Enhanced Feature Page)
12	-	-	-	-	-	-	-	FD9
Page 3 - Autocalibration Registers
12	D7	D6	D5	D4	D3	D2	D1	D0
13	-	A6	A5	A4	A3	A2	A1	A0
14	0	TDBUSY	EEBUSY	CMUXEN	TDACEN	0	0	0
15	REV
Page 4 - dsPIC Interface (Enhanced Feature Page)
12	PICD7	PICD6	PICD5	PICD4	PICD3	PICD2	PICD1	PICD0
13	I2CBUSY	-	-	PICA4	PICA3	PICA2	PICA1	PICA0
14	-	-	-	ACHOLD	PICPRST	ACERR	ACACT	PICBSY
15	-	-	-	-	-	-	-	PGDR
Page 5 - D/A Waveform Generator (Enhanced Feature Page)
12	-	-	-	-	-	-	-	-
13	-	-	-	-	-	-	-	-
14	DEPTH3	DEPTH2	DEPTH1	DEPTH0	WGCH1	WGCH0	WGSRC1	WGSRC0
15	-	-	-	-	-	-	-	-

I/O Register Definitions

Note: In the register descriptions, below, writes to an undefined bit have no effect. Reads of an undefined bit return the value zero.

Main Register Set Definitions

Start A/D Conversion: Base+0 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	ADSTART

ADSTART	Writing any value to this register starts an A/D conversion, unless a conversion is already in progress (AD_BUSY high). An A/D conversion starts even if the board is set up for interrupt, DMA or external trigger mode.

A/D LSB (bits 7-0): Base+0 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	AD7	AD6	AD5	AD4	AD3	AD2	AD1	AD0

AD7-AD0	A/D data bits 7 - 0; AD0 is the LSB.

Auxiliary Digital Output: Base+1 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	-	LED	DOUT2	DOUT1	DOUT0

LED	Toggles the on-board user LED; 1 = on, 0 = off.
DOUT2-0	Auxiliary digital output bits on analog I/O header CN12. Two pins also serve as optional counter outputs based on control register bits at Base+10:DOUT2 - CN12, pin 28. Counter 2 output when OUT2EN = 1 (Base+10, bit 5).DOUT1 - CN12, pin 30.DOUT0 - CN12, pin 27. Counter 0 output when OUT0EN = 1 (Base+10, bit 4).

A/D MSB (bits 15-8): Base+1 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	AD15	AD14	AD13	AD12	AD11	AD10	AD9	AD8

AD15-8	A/D data bits 15 - 8; AD15 is the MSB.

A/D Low Channel: Base+2 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	L4	L3	L2	L1	L0

L4-L0	The low channel number setting in the A/D channel scan range. Channel numbers range from 0 to 31 in single-ended mode. Writing to this register updates the current channel internal register.

A/D high Channel: Base+3 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	H4	H3	H2	H1	H0

H4-H0	The high channel number setting in the A/D channel scan range. Channel numbers range from 0 to 31 in single-ended mode.

DAC LSB: Base+4 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	DA7	DA6	DA5	DA4	DA3	DA2	DA1		DA0

DA7-DA0	D/A data bits 7 - 0 for the channel currently being accessed. This register is a holding register. Writing to it does not affect any D/A channel until the MSB is written. When the MSB is written (see below, Base+5), the value written to that register, along with the value written to this register, are simultaneously written to the D/A chip’s load register for the selected channel. See Base+5, write for more details.

Status/Auxiliary Digital Inputs: Base+4 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	DACBUSY	CALBUSY	ACACT	-	DIN3	DIN2	DIN1	DIN0

DACBUSY	The D/A serial transfer is in progress. Do not attempt to write to the D/A converters at Base + 4 or Base + 5 while this bit is high. This bit must be checked before any write to these registers.
CALBUSY	Calibration is in progress or EEPROM is being accessed. Do not attempt calibration or EEPROM access while this bit is high. This bit must be checked before any calibration or EEPROM operation is attempted.
ACACT	This is a copy of the value found at Page 4, Base+14, bit 1. It is mirrored at this location to provide a page-independent means of seeing the AC status, since AC uses Page 3.
DIN3-DIN0	Auxiliary digital inputs on analog I/O header J3. These pins have multiple functions based on control bits at Base + 9 and Base + 10:DIN3 - CN12, pin 31. External A/D clock when CLKSEL = 1 (Base + 9 bit 0)DIN2 - CN12, pin 32. Gate for counters 1 and 2 when GT12EN = 1 (Base + 10 bit 0)DIN1 - CN12, pin 26. Gate for counter 0 when GT0EN = 1 (Base + 10 bit 2)DIN0 - CN12, pin 25. Clock for counter 0 when SRC0 = 1 (Base + 10 bit1).

DAC MSB + Channel: Base+5 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	DACH1	DACH0	DASIM	DAGEN	DA11	DA10	DA9		DA8

DACH1-0	Binary number of the D/A channel, 3 – 0.
DASIM	D/A simultaneous update.NOTE: If enhanced features are disabled this is always ‘0’ for backwards compatibility, meaning that D/A outputs will update on every write to this register.1 = Latches D/A channel and output. Output will not change until this register is written to again with DASIM set to 0.0 = Perform D/A simultaneous update. All previously latched D/A channels and and current channel will update.
DAGEN	D/A wave form generator enableNOTE: If enhanced features are disabled this is always ‘0’.1 = Data is transferred to the D/A wave form memory block instead of the DAC chip. Used in conjunction with D/A wave form generator to store DAC code.0 = Data is transferred to the DAC chip for output.
DA11-8	D/A bits 11 - 8 for the selected output channel; DA11 is the MSB

FIFO Threshold Read-back (bit 8): Base+5 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	-	-	-	-	FD9

FD9	FIFO threshold (bit 9). (See FIFO Threshold: Base+6, below)

FIFO Threshold: Base+6 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	FD8	FD7	FD6	FD5	FD4	FD3	FD2	FD1

FD8-FD1	FIFO threshold (bits 1-8). This is the level at which the board will generate an interrupt request when the FIFO is enabled (FIFOEN = 1 in Base + 7). Note that the value written is shifted by 1 bit, i.e. divided by 2. For example, if you want a FIFO threshold of 256 samples, write a 128 to this register.The interrupt routine must read exactly this number of samples out each time it runs. The last time the routine runs, it should read whatever is remaining in the FIFO by monitoring the EF bit (Empty Flag) in the FIFO status register at Base + 7. When the FIFO is empty, EF = 1, and the FIFO returns the value hex FF on all read operations.If you are sampling at a slow rate or want to control when the interrupt occurs, you can set the threshold to a low value. For example, if you are sampling 16 channels at 10Hz and you want an interrupt each set of samples, you can set the threshold to 16 (write an 8 to this register), so that an interrupt will occur each 16 samples. Then the interrupt routine should read out 16 samples from the FIFO, and you get new data as soon as it is available.For higher sample rates (100KHz or higher) it may be necessary to increase the threshold above 256, to around 350 or even 512 with enhanced features enabled. If you set the threshold too high, you may overrun the FIFO, since the interrupt routine may not respond before the remaining locations are filled, causing an overflow. An overflow can be detected by checking the OVF bit in the FIFO status register at Base + 7. The correct threshold for your application can only be determined by testing.

FIFO Control: Base+7 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	-	FIFOEN	SCANEN	FIFORST	-

FIFOEN	FIFO enable:1 = Enable FIFO operation; if interrupts are enabled, interrupts will occur when the FIFO hits threshold (TF = 1). This slows down the interrupt rate dramatically compared to the actual A/D sample rate.0 = Disable FIFO operation; if interrupts are enabled, interrupts will occur after each A/D conversion.
SCANEN	Scan enable:1 = Scan mode enabled; FIFO will fill up with data for a single scan, and STS will stay high until entire scan is complete; if interrupts are enabled, interrupts will occur on integral multiples of scans.0 = Scan mode disabled; The STS bit will correspond directly to the status indicator from the A/D converter.
FIFORST	FIFO reset:1 = Reset FIFO; after this command is issued, EF = 1, TF = 0, FF = 0.0 = No function.

FIFO Status: Base+7 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	EF	TF	FF	OVF	FIFOEN	SCANEN	PAGE1	PAGE0

EF	Empty flag:1 = FIFO is empty.0 = FIFO is not empty.
TF	Threshold flag:1 = FIFO is at or beyond threshold; if the FIFO threshold is 256 words, this flag is set when the FIFO contains at least 256 words of A/D data.0 = FIFO is less than threshold.
FF	Full flag:1 = FIFO is full; the next A/D conversion will result in an overflow.0 = FIFO is less than full.
OVF	Overflow flag:1 = FIFO has overflowed; data has been lost. This flag is cleared on the next successful A/D read.0 = FIFO has not overflowed since the last A/D data read.
FIFOEN	FIFO enable read-back.
SCANEN	Scan enable read-back.
PAGE0-1	Read-back of the current page register setting. (See Base+8 below)

Miscellaneous and Page Control: Base+8 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	RESETA	RESETD	INTRST	P2	P1	P0

RESETA	Writing a 1 to this bit causes a full reset of all features of the board, including the DACs, the FIFO, the digital I/O, and all internal registers. The counter/timers are not affected by this reset.
RESETD	Writing a 1 to this bit causes a reset identical to above except the analog outputs are not affected.
INTRST	Writing a 1 to this bit resets the interrupt request circuit on the board. The programmer must write a 1 to this bit during the interrupt service routine, or further interrupts will not occur. Writing a 1 to this bit does not disturb the values of the PAGE bits.
P2-P0	Three-bit value that selects which I/O device is accessible through the registers at locations Base + 12 through Base+15:

P<2:0>	Page	Device
000	0	8254
001	1	8255
010	2	FIFO Control
011	3	EEPROM/TrimDAC
100	4	dsPIC
101	5	D/A Waveform Generator
110	6	Factory Use Only
111	7	Not Used

Pages 2, 4, 5, 6 and 7 are only accessible when the enhanced features are enabled. Note that P2 is an enhanced feature bit.Writing to the page bits will not generate a board reset or interrupt reset, as long as those bits are kept at 0 in the data written to this register.

A/D Status: Base+8 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	STS	S/D1	S/D0	ADCH4	ADCH3	ADCH2	ADCH1	ADCH0

STS	A/D chip status:1 = A/D conversion or A/D scan in progress.0 = A/D idle.
S/D1-0	Single-ended / Differential A/D input mode indicator. S/D1 controls the channels 8-15 and 24-31, S/D0 controls 0-7 and 16-23.1 = Single-ended (default).0 = Differential.
ADCH4-0	Current A/D channel; this is the channel currently selected on board and is the channel that will be used for the next A/D conversion (unless a new value is written to the low channel register).

Interrupt and A/D Clock Control: Base+9 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	ADINTE	DINTE	TINTE	RSVD1	DMAEN	-	CLKEN	CLKSEL

ADINTE	A/D interrupt enable:1 = Enable A/D interrupt operation.0 = Disable A/D interrupt operation.
DINTE	Digital interrupt enable:1 = Enable digital I/O interrupt operation.0 = Disable digital I/O interrupt operation.
TINTE	Timer 0 interrupt enable:1 = Enable counter/timer 0 interrupt operation.0 = Disable counter/timer 0 interrupt operation.
RSVD1	Reserved for future use
DMAEN	DMA Enable. This bit is ignored if enhanced features are disabled. See DMA signal definition for more detail on DMA behavior.1 = DMA Enabled.0 = DMA Disabled.
CLKEN	Enable hardware clock for A/D sampling:1 = Enable hardware clock for A/D (source is selected with CLKSEL bit below);NOTE: When this bit is 1, software triggers are disabled, i.e. writing to Base + 0 will not start an A/D conversion.0 = Disable hardware clocking for A/D; A/D conversions occur with software command only.
CLKSEL	Hardware clock select (enabled only when CLKEN = 1 above):1 = Internal clock: Falling edges on the output of counter/timer 2 generate A/D conversions. Counter 2 is in turn driven by counter 1, which is driven by the clock selected by bit FREQ12 in Base + 10 below.0 = External trigger: Falling edges on the DIN3/EXTCLK pin on the I/O header generate A/D conversions.

Interrupt and A/D Clock Status: Base+9 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	ADINT	DINT	TINT	-	DMAEN	P2	CLKEN	CLKSEL

ADINT	A/D interrupt status; Cleared by writing to INTRST (Base+8).1 = A/D interrupt request has occurred.0 = No interrupt request.
DINT	Digital interrupt status; Cleared by writing to INTRST (Base+8).1 = Digital interrupt request has occurred.0 = No interrupt request.
TINT	Timer interrupt status; Cleared by writing to INTRST (Base+8).1 = Timer interrupt request has occurred.0 = No interrupt request.
DMAEN	Read-back of control register bit defined, above.
P2	Read-back of P2 register bit defined at Base+8/write.
CLKEN	Read-back of control register bit defined, above.
CLKSEL	Read-back of control register bit defined, above.

Counter/Timer and DIO Control: Base+10 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	FREQ12	FREQ0	OUT2EN	OUT0EN	RSVD	GT0EN	SRC0	GT12EN

FREQ12	Input frequency select for the counter 1-2 cascade:1 = Input to counter 1 is a 100KHz (one hundred, not ten) frequency derived from the on-board 10MHz oscillator.0 = Input to counter 1 is 10MHz from the on-board oscillator.
FREQ0	Input frequency select for counter 0 when SRC0 = 1 (bit 1):1 = Input to counter 0 is a 10KHz (ten, not one hundred) frequency derived from the on-board 10MHz oscillator.0 = Input to counter 0 is 10MHz from the on-board oscillator.
OUT2EN	Counter/timer 2 output enable:1 = Counter 2 output appears on I/O header CN12, pin 28.0 = CN12, pin 28, is controlled by bit DOUT0 at Base+1.
OUT0EN	Counter/timer 0 output enable:1 = Counter 0 output appears on I/O header CN12 pin 27, OUT 0 / DOUT 0.0 =.OUT 0 / DOUT 0 pin is set by bit DOUT0 at Base+1.
RSVD	Reserved for future use
GT0EN	Counter/timer 0 gate enable:1 = Gate 0 / DIN 1, CN12 pin 26, acts as an active high gate for counter/timer 0. This pin is connected to a 10KΩ pull-up resistor.0 = Counter/timer 0 runs freely with no gating.
SRC0	Counter 0 input source:1 = Input to Counter 0 is the clock determined by FREQ0 (bit 6).0 = Input to Counter 0 is CN12 pin 25 (CLK 0 / DIN 0). The falling edge is active. This pin is connected to a 10KΩ pull-up resistor.
GT12EN	Counter/timer 1/2 and external trigger gate enable:This bit enables gating for A/D sampling for both internal and external clocking.1 = When CN12 pin 32 (EXTGATE / DIN 2) is low prior to the start of A/D conversions, A/D conversions will not begin until it is brought high (trigger mode).If the pin is brought low while conversions are occurring, conversions will pause until it is brought high (gate mode). CN12 pin 32 is connected to a 10KΩ pull-up resistor.0 = The interrupt operation begins immediately once it is set up and the selected clock source begins, with no external triggering or gating.

Analog Configuration: Base+11 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	SCINT1	SCINT0	RANGE	ADBU	G1	G0

SCINT1-0	Scan interval. This is the time between A/D samples when performing a scan (SCANEN = 1). The driver sets a default of 10μs.

SCINT1	SCINT0	Interval
0	0	20µS
0	1	15µS
1	0	10µS
1	1	4µS

RANGE5V or 10V A/D positive full-scale voltage (0 = 5V, 1 = 10V) ADBUA/D bipolar/unipolar setting; 0 = bipolar, 1 = unipolar. These control bits define the A/D input range for a gain setting of 1.

RANGE	ADBU	A/D Range
0	0	+/- 5V
0	1	0-5V
1	0	+/- 10V
1	1	0-10V

G1-0A/D programmable gain amplifier setting:

G1	G0	Gain
0	0	1
0	1	2
1	0	4
1	1	8

The gain setting is the ratio between the full-scale voltage range at the A/D converter and the full-scale voltage range at the input to the board. The gain should never cause the input signal to exceed the range of the A/D, because incorrect measurements will result (clipping).The A/D full-scale voltage range is defined by the RANGE and ADBU bits above. To calculate the optimum gain setting, select the highest gain that does not allow the input signal to exceed the selected A/D range over its entire expected fluctuation range. Note that these settings can be changed at any time, even between A/D conversions, so you can tune the board’s settings to each input signal.Note: On power up or system reset, the board is configured for A/D bipolar mode, input range = ±5V, and gain = 1, corresponding to all zeros in this register.

Analog I/O Read-back: Base+11 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	WAIT	RSVD	SCINT1	SCINT0	RANGE	ADBU	G1	G0

WAIT	Analog input circuit settling time holdoff indicator:1 The analog input circuit is settling on a new signal and is not yet ready for a new conversion to start; this will occur each time you change the channel, gain, or input range on the board. The wait time is approximately 10μS.0 The analog input circuit has settled, and a new A/D conversion may begin.
RSVD	Reserved for future use.
SCINT1-0	Read-back of control bit described, above. Only available if enhanced features are enabled.
RANGE	Read-back of control bit described, above.
ADBU	Read-back of control bit described, above.
G1-0	Read-back of control bit described, above.

Page 0 Register Definitions

This section is included as a reference to the page 0 counter/timer registers. Behavior of these registers should be identical to the 82C54 counter/timer chip. Please, read the 82C54 datasheet, for this behavior.

Counter 0 Data: Base+12 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	CTR0D7	CTR0D6	CTR0D5	CTR0D4	CTR0D3	CTR0D2	CTR0D1	CTR0D0

CRT0D7-0	Counter 0 data.

Counter 1 Data: Base+13 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	CTR1D7	CTR1D6	CTR1D5	CTR1D4	CTR1D3	CTR1D2	CTR1D1	CTR1D0

CRT1D7-0	Counter 1 data.

Counter 2 Data: Base+14 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	CTR2D7	CTR2D6	CTR2D5	CTR2D4	CTR2D3	CTR2D2	CTR2D1	CTR2D0

CRT2D7-0	Counter 2 data.

82C54 Control: Base+15 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	SC1	SC0	RW1	RW0	M2	M1	M0	BCD

SC1-0	Counter select.
RW1-0	Read/write mode.
M2-0	Timer mode.
BCD	Binary Coded Decimal counter.

Page 1 Register Definitions

This section is included as a reference to the page 1 82C55-like digital I/O registers.

DIO Port A I/O: Base+12 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	A7	A6	A5	A4	A3	A2	A1	A0

A7-A0	Port A data.

DIO Port B I/O: Base+13 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	B7	B6	B5	B4	B3	B2	B1	B0

B7-B0	Port B data.

DIO Port C I/O: Base+14 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	C7	C6	C5	C4	C3	C2	C1	C0

C7-C0	Port C data.

DIO Control: Base+15 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	1	MODEC	MODEA	DIRA	DIRCH	MODEB	DIRB	DIRCL

MODEC-A	Mode configuration bits. These must be set to 0.
DIRA DIRCH DIRB DIRCL	Direction control bits. On ports A and B, all the bits in each port must be the same direction. On port C, the upper half C7–C4 can have a different direction than the lower half C3–C0.0 = Output.1 = Input.

Note: Bit 7 must be set to 1. This indicates port configure mode in the 8255 (as opposed to bit set mode, which is not supported).

Page 2 Register Definitions

This is an enhanced features page. It is only accessible when enhanced features are enabled.

Expanded FIFO Depth: Base+12 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	-	-	-	-	FD9

FD9	This bit is used when setting the FIFO threshold. See the documentation for register Base+6 for more information.

Page 3 Register Definitions

These registers are used to control the auto-calibration process. For user software-controlled auto-calibration, these registers are used by the Universal Driver software or the user’s software to manage the calibration process. For auto-auto-calibration, the on-board dsPIC microcontroller uses these registers to manage the auto-calibration automatically.

EEPROM/TrimDAC Data: Base+12 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	D7	D6	D5	D4	D3	D2	D1	D0

D7-D0	Calibration data to be read or written to the EEPROM and/or TrimDAC.During EEPROM or TrimDAC write operations, the data written to this register will be written to the selected device.During EEPROM read operations this register contains the data to be read from the EEPROM and is valid after EEBUSY = 0.The TrimDAC data cannot be read back.

EEPROM/TrimDAC Address: Base+13 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	A6	A5	A4	A3	A2	A1	A0

A6-A0	EEPROM/TrimDAC address.The EEPROM recognizes address 0 – 127 using address bits A6 – A0 of this register. The TrimDAC only recognizes addresses 0 – 7 using bits A2 – A0. In each case, remaining address bits will be ignored.

Calibration Control: Base+14 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	EE_EN	EE_RW	RUNCAL	MUXEN	TDACEN	-	-	-

EE_EN	EEPROM Enable. Writing a 1 to this bit will initiate a transfer to/from the EEPROM as indicated by the EE_RW bit.
EE_RW	Selects read or write operation for the EEPROM: 0 = Write, 1 = Read.
RUNCAL	Writing 1 to this bit causes the board to reload the calibration settings from EEPROM.
MUXEN	Calibration multiplexor enable. The cal mux is used to read precision on-board reference voltages that are used in the autocalibration process. It also can be used to read back the value of analog output 0.1 enable cal mux and disable user analog input channels.0 disable cal mux, enable user inputs.
TDACEN	TrimDAC Enable. Writing 1 to this bit initiates a transfer to the TrimDAC (used in the autocalibration process).

Calibration Status: Base+14 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	0	TDBUSY	EEBUSY	CMUXEN	TDACEN	0	0	0

TDBUSY	TrimDAC busy indicator:0 = User may access TrimDAC.1 = TrimDAC is being accessed; user must wait.
EEBUSY	EEPROM busy indicator:0 = User may access EEPROM.1 = EEPROM is being accessed; user must wait.
CMUXEN	Calmux enable status:0 = Calibration multiplexor is not currently enabled.1 = Calibration multiplexor is enabled and may be updated.
TDACEN	TrimDAC enable status:0 = TrimDAC is not enabled.1 = TrimDAC is enabled and may be updated.

Advanced Feature Access: Base+15 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	EE_ACC

EE_ACC	EEPROM access. After entering page 3 by setting the Page bits, the user must write the value 0xA5 (binary 10100101) to this register in order to get access to the EEPROM. This helps prevent accidental corruption of the EEPROM contents. Once the page is set and this value is written, you can make unlimited reads and writes to the EEPROM without resending this key as long as you stay on page 3.Writing 0xA6 to this register enables all enhanced features and sets A/D FIFO depth to 1024 samples. This enhanced feature state remains in effect until explicitly disabled.Writing 0xA7 to this register disables all enhanced features. This is the default power-on state. Writing 0xA7 to this register automatically halts any enhanced feature currently running, internally clears all enhanced registers to their default state, and resets the A/D FIFO depth to 512.

FPGA Revision Code: Base+15 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	REV

REV	This register is the revision level of the FPGA design. This value changes with new versions of the FPGA. It provides a way to distinguish between different versions of FPGA code.

Page 4 Register Definitions

This is an enhanced features page. It is only accessible when enhanced features are enabled.

dsPIC Data: Base+12 (Read/Write)


Bit:	7	6	5	4	3	2	1	0
Name:	PICD7	PICD6	PICD5	PICD4	PICD3	PICD2	PICD1	PICD0

PICD7-0	Data to read/write to/from the PIC microcontroller. The data must be written to this register before the address and read/write bit is written to Base+13, below.

dsPIC Address: Base+13 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	PICR/W	-	-	PICA4	PICA3	PICA2	PICA1	PICA0

PICR/W	Read/write control: 0 = write, 1 = read.
PICA4-0	dsPIC internal address.Writing a byte with R/W = 0 causes the dsPIC to write the data contained in the dsPIC Data Register, above, to the dsPIC internal address indicated by PICA4-0.Writing a byte with R/W = 1 causes the dsPIC to read the data at dsPIC internal address, PICA4-0, and places the received data in the dsPIC Data Register.

dsPIC Address Read-back: Base+13 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	I2CBUSY	-	-	PICA4	PICA3	PICA2	PICA1	PICA0

I2CBUSY	I2C port status bit:0 = Last I2C operation completed.1 = Last I2C operation in progress.
PICA4-0	dsPIC address last accessed.

Auto-calibration Command: Base+14 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	ACHOLD	ACREL	PICRST	ACABT	ACTRIB

ACHOLD	Auto-autocal process is disabled. Autocalibration must be triggered by software.
ACREL	Auto-autocal process is enabled. Auto-autocalibration will occur whenever the board requires it.
PICRST	Reset dsPIC device. This command is normally not needed.
ACABT	Abort any currently running auto-autocal operation immediately.
ACTRIB	Initiate an auto-autocal process immediately.

Note: Set the desired bit to a value of 1 to execute the desired command. Only one bit can be set to 1 at a time. Bits are processed MSB to LSB. The first 1 bit determines which command is executed.

Auto-calibration Status: Base+14 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	ACHOLD	PICPRST	ACERR	ACACT	PICBSY

ACHOLD	1 = dsPIC in holdoff mode (auto-autocal disabled).
PICPRST	1 = dsPIC device present on board.
ACERR	1 = dsPIC detected errors during last Auto-autocal process.
ACACT	1 = Auto-autocal process currently in progress.
PICBSY	1 = dsPIC busy, either with auto-autocal or some other activity.

dsPIC Programming Control: Base+15 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	PSTART	PSTOP	PGDOUT	PGDIN	PGDW1	PGDW0	PGCW1	PGCW0

PSTART	Drive EN_PROG# signal low.
PSTOP	Drive EN_PROG# high.
PGDOUT	FPGA makes PIC_PGD line an output, but leave at current level (i.e. perform input to find current level, set line as an output at same level).
PGDIN	FPGA makes PIC_PGD line an input.
PGDW1	If PIC_PGD line is in output mode, set high.
PGDW0	If PIC_PGD line is in output mode, set low.
PGCW1	Set PIC_PGC line high.
PGCW0	Set PIC_PGC line low.

Note: This register is used to control the on-board dsPIC microcontroller. The dsPIC controls the auto-autocalibration process, and it also provides the communication link between the board and its serial port. Only one bit can be set to 1 at a time. Bits are processed MSB to LSB. The first 1 bit determines which command is executed.

dsPIC Programming Status: Base+15 (Read)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	-	-	-	-	PGDR

PGDR	Reads back current level of PIC_PGD line (low = 0, high = 1).

Page 5 Register Definitions

This is an enhanced features page. It is only accessible when enhanced features are enabled.

Waveform Buffer Address (LSB): Base+12 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	DACA7	DACA6	DACA5	DACA4	DACA3	DACA2	DACA1	DACA0

DACA7-0	LSB of address to store D/A code in D/A waveform buffer.

Waveform Buffer Address (MSB): Base+13 (Write)


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	-	-	-	DACA9	DACA8

DACA9-8	MSB of address to store D/A code in D/A waveform buffer.

Waveform Generator Control: Base+14 (Read/Write)These two bits combine to choose how many codes are output on each frame.


Bit:	7	6	5	4	3	2	1	0
Name:	DEPTH3	DEPTH2	DEPTH1	DEPTH0	WGCH1	WGCH0	WGSRC1	WGSRC0

DEPTH3-0	These bits define the size of the D/A waveform buffer. The depth is based on this equation: Depth = [(DEPTH3-0) + 1] * 64 This allows valid depth values from 64 to 1024 samples.The waveform generator frame pointer will return to 0 whenever it hits either 1024 or the depth value indicated above.
WGCH1-0

WGCH1	WGCH0	Description
0	0	One code per frame
0	1	Two codes per frame
1	X	Four codes per frame

WGSRC1-0These two bits combine to choose which trigger source is used to increment the waveform by one frame.

WGSRC1	WGSRC0	Description
0	0	Manual (using WGINC)
0	1	Counter 0 output
1	0	Counter 1/2 output
1	1	External trigger (CN12, pin 31)

Waveform Generator Command: Base+15 (Write) WGRST.


Bit:	7	6	5	4	3	2	1	0
Name:	-	-	-	-	WGINC	WGRST	WGPS	WGSTRT

WGINC	Begin or resume the waveform generator.
WGRST	Pause/stop the waveform generator. The current position in memory is saved for the next begin/resume, or can be reset using
WGPS	Reset the waveform generator to output from the beginning of the D/A code buffer.
WGSTRT	Force the waveform generator to increment one frame.

Note: Only one bit can be set to 1 at a time. Bits are processed MSB to LSB. The first 1 bit determines which command is executed.